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Configurable, Field-level Auditing for Spring and Hibernate

1 Configurable, Field-level Auditing for Spring and Hibernate Jim Majure, Majure Consulting, LLC (jim@majureconsulting.com) Table of Contents Background ..... 1 The Audit ...

Power Transducer Series 50 - PTA50, PTV50, without power ...

Data Sheet 3KDE485000R1001 Power Transducer Series 50 PTA50, PTV50, without power supply; PTM50, with power supply; PTK50-1, PTK50-3, configurable;

eWON500™ The Configurable Gateway - User Guide PURPOSE

eWON500™ The Configurable Gateway ver 1.0 9/11/05 Page 1 User Guide PURPOSE You have just received your brand new eWON500™! ACT’L produces a complete range of Ethernet/Internet

Design Productivity for Configurable Computing∗

Design Productivity for Configurable Computing ∗ Brent Nelso n 1, Michael Wirthlin 1, Brad Hutchings 1, Peter Athanas 2, Shawn Bohner 2 1 Brigham Young University and 2 Virginia Tech { nelson, wirthlin, hutch } @ee.byu.edu, { athanas, sbohner } @vt.edu May 13,2008 Abstract Abstract goes here ...

A Research Agenda for Improving Configurable Computing Design ...

A Research Agenda for Improving Configurable Computing Design Productivity Executive Summary 2008 FPGA Tool-Flow Workshop, Salt Lake City, UT Mike Wirthlin, BYU Brent Nelson, BYU Brad Hutchings, BYU Peter Athanas, VT Shawn Bohner, VT This report summarizes the results of a research study group ...

DIGITAL_IO Configurable Digital IO Module

DIGITAL_IO Configurable Digital IO Module Summary Core Reference CR0179 (v1.0) August 29, 2007 This document describes how to place and use the configurable DIGITAL IO virtual instrument in an FPGA design.

SEL-311C-1, -2 Transmission Protection System Configurable Labels

Date Code 20110224 SEL-311C-1, -2 Transmission Protection System Configurable Labels SEL-311C-1, -2 Transmission Protection System Configurable Labels Overview These instructions apply to all SEL-311C Transmission Protection System relays with Ethernet and configurable labels.

Configurable Hardware Design for Frequency-Diverse Target ...

Configurable Hardware Design for Frequency-Diverse Target Detection Joshua Weber, Erdal Orukluand Jafar Saniie Department of Electrical and Computer Engineering Illinois Institute of Technology Chicago, Illinois 60616 Abstract —In this paper, we present a reconfigurable hardware architecture ...

Fast Configurable-Cache Tuning with a Unified Second- Level Cache

Fast Configurable-Cache Tuning with a Unified Second-Level Cache ABSTRACT Tuning a configurable cache subsystem to an application can greatly reduce memory hierarchy energy consumption.

Virtex-6 FPGA Configurable Logic Blocks

Virtex-6 FPGA CLB User Guide www.xilinx.com UG364 (v1.1) September 16, 2009 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices.